Switched capacitor integrators are widely used and a known problem with such circuits is the existence of output voltage errors resulting from charge injection by parasitic capacitances. Parasitic capacitance is associated with the inputs of an integrating amplifier and may exist from a variety of sources. A common source of parasitics is a conventional transistor switch known as a transmission gate wherein two transistors of complementary conductivity are coupled in parallel and controlled or clocked by complementary signals. Such parasitics results from gate-drain and gate-source overlap capacitances and drain-substrate and source-substrate junction capacitances. Other have attempted to minimize parasitics associated with transistor switches by adding compensating circuitry to the switches which often require at least one of additional control signals, additional circuitry or additional fabrication processing steps. Others have used transistor switches having a single transistor which is compensated for parasitic capacitance. However, typical single transistor switches when compensated have a high impedance when made conductive at low power supply voltages which degrades circuit performance. Regardless of the effectiveness of minimizing error charge injected into an amplifier by transistor switches, other errors result from parasitics existing between input nodes and noise sources such as power supplies and other signal lines. An example of a switched capacitor circuit which is compensated for stray capacitance errors is taught by Temes et al. in U.S. Pat. No. 4,543,534 entitled "Offset Compensated Switched Capacitor Circuits". A differential amplifier structure is taught by Temes et al. which has the known advantage of superior power supply rejection compared to single input differential amplifier. A disadvantage with differential amplifier structures and associated compensating circuitry is the large amount of circuitry typically required.